Integrated circuits are generally fabricated on a thin, circular silicon wafer or substrate. Semiconductor devices and electrical interconnections that form the integrated circuit are conventionally made by building many mask layers on top of one another on the substrate. Each successive mask layer may have a pattern that is defined using a mask. A mask has a shape used for processing features in a particular process step during fabrication. The mask layers are fabricated through a sequence of pattern definition steps using the masks, which are interspersed with other process steps such as oxidation, etching, doping and material deposition. When a mask layer is defined using a mask chosen or provided by a customer, the mask layer is programmed or customized.
The lowest, “base” layers include the active areas of the semiconductor devices, such as diffusion regions and gate oxide areas, and desired patterns of the polysilcon gate electrodes. One or more metal and insulating layers are then deposited on top of the base layers and patterned to form conductive segments, which interconnect the various semiconductor devices formed in the base layers. Electrical contacts or vias are formed to electrically connect a conductive segment of one of the metal layers with a conductive segment or semiconductor device on one of the other layers on the wafer.
An application specific integrated circuit (ASIC) is an integrated circuit designed specifically for a particular application or use. There are three categories of ASICs in terms of programmability of mask layers: fully programmable ASICs, non-programmable ASICs, and semi-programmable ASICs. In a fully programmable ASIC, all mask layers are programmed or customized. A typical example of a fully programmable ASIC is a cell-based ASIC (CBIC). In a non-programmable ASIC, none of the mask layers are programmed or customized, and all mask layers are pre-fabricated by an ASIC vendor. A typical example of a non-programmable ASIC is a field-programmable gate array (FPGA). In a semi-programmable ASIC, some, but not all, mask layers are programmable. A typical example of a semi-programmable ASIC is a gate-array-based ASIC. A semi-programmable ASIC can combine the high-density, high-performance benefits of standard-cell ASICs with the fast time-to-market and customization benefits of FPGAs.
Higher-level logic functions, such as phase-locked loops, are typically implemented as standard cells so they can be optimized for a desired operating frequency range. It is therefore common for ASIC vendors to include several versions of a phase-locked-loop cell, each with different operating characteristics, in a cell library so that the appropriate cell can be selected for a particular application. However, each PLL cell may have different base layer and metal layer patterns since they are implemented as standard cells. This increases the design and fabrication cycle times since the base layer masks and lower metal layer masks may change depending upon which PLL cell is selected.
Phase-locked loop cells are therefore desired, which allow for reduction in the design and fabrication cycle times associated with the implementation of these cells on a integrated circuit.